{"id":1222,"date":"2013-07-29T00:51:00","date_gmt":"2013-07-29T00:51:00","guid":{"rendered":"http:\/\/www.syslog.cl.cam.ac.uk\/?p=1222"},"modified":"2013-07-30T09:27:50","modified_gmt":"2013-07-30T09:27:50","slug":"liveblog-from-apsys-2013","status":"publish","type":"post","link":"https:\/\/www.syslog.cl.cam.ac.uk\/2013\/07\/29\/liveblog-from-apsys-2013\/","title":{"rendered":"Liveblog from APSYS 2013"},"content":{"rendered":"<p><a href=\"http:\/\/www.cl.cam.ac.uk\/~mpg39\/\">Matt<\/a> and myself are at the Asia-Pacific Systems Workshop today, presenting <a href=\"http:\/\/www.cl.cam.ac.uk\/~ms705\/pub\/papers\/2013-apsys-dios.pdf\">our paper<\/a> on distributed operating systems in data centers, and we'll be live-blogging the workshop for you.<\/p>\n<p><!--more--><\/p>\n<h2>Introduction<\/h2>\n<p>&nbsp;<\/p>\n<p><strong>Registration stats:<\/strong> only 60+ registrations this time (down from last time), 31% Singapore,\u00c2\u00a043% from rest of Asia, 17% North-America, 6% Europe and 3% Australia. 11 student travel grants awarded (with SIGOPS\/MSR support), up from 9 last time.<\/p>\n<p><strong>Program stats:<\/strong><\/p>\n<ul>\n<li>73 total, 28% up from previous record; especially Asia-Pacific submissions increased (by 73%); 53 total from Asia-Pacific region.<\/li>\n<li>Double reviewing load on PC as more than expected submissions.<\/li>\n<li>36 papers selected for discussion, 5 accepted outright, 15 discussed and re-ranked, ties broken by \"likelihood to generated discussion\"; face-to-face PC meeting planned, but not necessary as consensus was reached.<\/li>\n<li>20 total accepted papers, 11 from Asia-Pacific, 9 from elsewhere.<\/li>\n<li>27% acceptance ratio overall.<\/li>\n<li>PC 50-50 split between Asia-Pacific and U.S.\/rest-of-world.<\/li>\n<li>First time ever to give best paper\/best student paper awards -- to be announced at banquet.<\/li>\n<\/ul>\n<p>&nbsp;<\/p>\n<h2>Keynote:\u00c2\u00a0\u00e2\u20ac\u0153Can truly dependable systems be affordable?\u00e2\u20ac\u009d<\/h2>\n<p><em>Gernot Heiser, UNSW &amp; NICTA<\/em><\/p>\n<ul>\n<li>Running a sizeable project on system verification and trustworthyness. Why?<\/li>\n<li>Present day systems aren't trust worthy.<\/li>\n<li>Lot's of things have been hacked. ATMs, cars, pacemakers, drones.<\/li>\n<li>High assurance systems. Every line of code costs about $1000.<\/li>\n<li>eg: Pacemaker - RTOS + drivers + network stack + monitoring = 10,000's of lines of code.<\/li>\n<li>In high assurance domain, isolation provided by VMare\/Xen\/KVM etc. Isolation provided by 10,000's of lines of code.<\/li>\n<li>Best practice - separation kernels - small enough for a single programmer to understand.<\/li>\n<li>seL4 - mathematical proof of isolation - nice but .. what about cost sensitive environments?<\/li>\n<li>There is a refinement proof for seL4 from high level goals all the way down to the binary. Exclusions: Init, privileged state and caches, multicore.<\/li>\n<li>But what did it cost? 20.5 person years for refinement proof. \u00c2\u00a0Integrity: about 1py. Confidentiality: 4.5py Availablility: 0py. Binary and WC exec time about 2pys each. \u00c2\u00a0- Around $400 PLOC.<\/li>\n<li>In comparison to state of the art. High assurance $1000 loc - still no guarantees, low assurance $100-200loc, no guarantees.<\/li>\n<li>Estimate for a repeat is about half the cost -- about the same cost as doing L4::Pistachio.<\/li>\n<li>Note: seL4 is aggressively optimised -- easy because proofs can be rerun over night.<\/li>\n<li>What did we learn? - seL4 is probably about as secure as as existing kernel. BUT, there is a a foundation on which proof can now be founded allowing end-to-end trust, roughly the cost of traditional software.<\/li>\n<li>How? Combine theorem proving with synthesis and DSLs.<\/li>\n<li>Next step: High assurance drones. Modified arducopter.<\/li>\n<li>Inside: Mission board - seL4 + linux. \u00c2\u00a0Control board with a new verified RTOS generated by synthesis. Components connected via CAN bus. \u00c2\u00a0Distributed system is nice because it is real.<\/li>\n<li>Architecture: component architecture, using well known patters, glued together but auto generated \u00c2\u00a0from a DSLs and synthesis.<\/li>\n<li>More about synthesis - can synth drivers from a spec of the OS interface and the device interface.<\/li>\n<li>More about DSLs: glue code is trivial, file systems and network stacks. Should be able to generate these from DSLs.<\/li>\n<li>Files systems code has lots of error handling and marshinling code so should be able to generate this and reduce code size by 5x-10x.<\/li>\n<li>Using a DSL means you can use a generator to produce execution code and verification code. Much less work for the verifier, none of the boring bits.<\/li>\n<li>Using both DLS and synthesis means you can reduce the amount of effort to do full system verification.<\/li>\n<li>Vision: Verified high-level runtime - If you can verify the runtime, you only have to verify the the programs at the high level semantics -- which again gives a productivity boost.<\/li>\n<\/ul>\n<p>&nbsp;<\/p>\n<p>Conclusions:<\/p>\n<ul>\n<li><span style=\"line-height: 13px;\">Formal methods aren't that much more expensive than SOA for about 10K LOC<\/span><\/li>\n<li>We think we can scale bigger and cheaper if we componentise, synthesise and abstract with DSLs.<\/li>\n<li>Big challenge is proof composition.<\/li>\n<\/ul>\n<p>Questions:<\/p>\n<p>Q: What about proof maintenance? A: It's about the same effort as regular software.<\/p>\n<p>Q: Know how transfer. Very high level (expensive) skills required to do the proofs: A: True. Using the right techniques (DSLs\/synth etc), we can push this deeper into industry.<\/p>\n<p>Q: Can you techniques be adapted for Linux\/Windows? A: Yes. This is part of it. Linux synth'd drivers\/filesystems work already.<\/p>\n<p>Q: ARM trust zone? Comments? A: Trust zone is a hack. Limited in what it can do.<\/p>\n<p>Q: What's the limit? How far can you go? A: Intentionally only talking about 1 order of magnitude. Components make verification easier, but make the performance harder.<\/p>\n<p><em>(mpg39)<\/em><\/p>\n<p>&nbsp;<\/p>\n<h2>Session 1: OS and Performance I<\/h2>\n<p>&nbsp;<\/p>\n<h3>Schedule processes, not VCPUs!<\/h3>\n<p><i>Xiang Song, Jicheng Shi, Haibo Chen, Binyu Zang<br \/>\nInstitute of Parallel and Distributed Systems, Shanghai Jiao Tong University<\/i><\/p>\n<p>Many data centers use virtualization these days, and run multi-core VMs on top of multi-core CPUs. This leads to the classical problem of two-level scheduling: the hypervisor tries to schedule vCPUs over physical cores, and the guest OS tries to schedule processes over its vCPUs. The dilemma is that there is no information shared between these, and a semantic gap. Two key examples: vCPU preemption during a critical section (other vCPUs waiting for it e.g. in spinlock waste CPU time) and stacking (same issue, except with a vCPU blocked on another (I think?).<\/p>\n<p>Some indicative numbers on the streamcluster benchmark shows that overheads of 2.5-5x (KVM) and 2-4x (Xen) are not uncommon when using 2-4 VMs on a 12-core Intel machine. Somewhat counter-intuitively, having a 12-vCPU VM run atop a 12-core machine may end up performing worse than a 6-vCPU one (on wordcount\/histogram benchmark).<\/p>\n<p>The solution proposed is\u00c2\u00a0<em>VCPU ballooning<\/em>: exclude the hypervisor from dynamic vCPU scheduling (basically seems to be pinning vCPUs to pCPUs), and decide the number of vCPUs for each VM according to some weight. Might need to balloon vCPUs, i.e. take them offline e.g. when VMs are migrated\/deleted\/created. There are existing solutions to this that have some problems. One counter-argument to vCPU ballooning is that applications might try to optimize the number of threads independently, and end up with a thread-vCPU mismatch, but they argue that this isn't a big deal: long-running server applications can typically adapt to CPU hotplug, and short-running applications will only be unbalanced for a short time.<\/p>\n<p>Evaluation: some benchmarks from PARSEC and Phoenix MapReduce; vCPU ballooning achieves 3-35% speedup over Xen credit scheduler, while the affinity scheduler sometimes even degrades performance. Same picture with KVM, and less time spent in kernel in general. &gt;100% speedup on Xen and KVM for Phoenix histogram\/wordcount for their vCPU ballooning scheduler, while affinity scheduler degrades by a few percent.<\/p>\n<p>Q (Nickolai Zeldovich): Why isn't using the hotplug support in the OS a good idea?<br \/>\nA: Xen supports hotplug insertion, but not removal. KVM does not support it in the simulator (?).<\/p>\n<p><em>(ms705)<\/em><\/p>\n<p>&nbsp;<\/p>\n<h3>Exploring Microcontrollers in GPUs<\/h3>\n<p><i>Yusuke Fujii, Takuya Azumi, Nobuhiko Nishio, &amp; Shinpei Kato<br \/>\nRitsumeikan University &amp; Nagoya University<\/i><\/p>\n<p>GPGPUs are jolly good, and their performance keeps increasing very quickly. Now looking at 1500+ cores on nVidia Kepler GPUs. GFLOPS performance scales linearly, and importantly much faster than CPU performance (at much better performance per Watt). Great, if you have the right applications!<\/p>\n<p>Much current research looks at OS support for GPUGPUs, e.g. Gdev (USENIX ATC '12). But GPUs still aren't sufficiently \"general-purpose\". The mean reason for this is that they do not do multitasking well, as they can't manage resource arbitration. So instead, resources are managed by the CPU in kernel-space. So in this work, they focus on putting a resource manager into GPU hardware, in order to avoid having to cross the boundary for resource management all the time. But modifying GPU hardware is hard due to closed-source \"black-box\" nature. Fortunately, the nouveau driver people are doing a pretty decent job at reverse-engineering the hardware and specs.<\/p>\n<p>One thing that it looks like the found is that GPUs have a bunch of microcontrollers inside them, which have programmable firmware that can be replaced. But it's hard to do so -- must write assembly code for an undocumented black box. In this work, they provide a development environment for GPU firmware (compiler suite), build some firmware and add new features that leverage the microcontrollers.<\/p>\n<p>They are porting the GUC framework (this seems to be an existing nVidia assembly thing from nouveau) to the LLVM infrastructure, so that one can write in any front-end and get GUC assembly from the backend (which they added). Obvious benefits of easier development, higher productivity etc. fall out.<\/p>\n<p>Using this suite, they developed a \"baseline\" firmware that has the same features as the default, but exposes a bunch of microcontroller details (not clear how). In the extended version, they add microcontroller-based data transfer functionality for DMA from host memory to GPU memory.<\/p>\n<p>Evaluation: compare basic firmware performance, find that theirs is as good as nVidia default and nouveau firmware. When comparing the data transfer performance between various existing mechanisms and their newly implemented method. They seem to to mostly lose out against conventional methods in serial data transfer (apart from a narrow transfer size range), but win by a small margin in the concurrent data transfer case.<\/p>\n<p>Future work: resource management using microcontrollers!<\/p>\n<p>&nbsp;<\/p>\n<p>Q: Why is there such large error bars in the evaluations?<br \/>\nA: PCIe and GPU memory variation.<\/p>\n<p>Q (Malte Schwarzkopf, Cambridge): Most of the time conventional is better, why do you only win sometimes?<br \/>\nA: We're not sure why. But our methods can be used concurrently with current methods.<\/p>\n<p>Q (Stefan Bucur, EPFL): How much of the black box reverse engineering work can be applied to other work? E.g. Radeons?<br \/>\nA: No, although they have microcontrollers too, so some principles might be transferrable.<\/p>\n<p><em>(ms705)<\/em><\/p>\n<p>&nbsp;<\/p>\n<h3>Opportunities and pitfalls of multi-core scaling using Hardware Transaction Memory<\/h3>\n<p><i>Zhaoguo Wang, Hao Qian, Haibo Chen &amp; Jinyang Li<br \/>\nFudan University, Shanghai Jiao Tong University, New York University<\/i><\/p>\n<p>Many people use coarse-grained locks for mutual exclusion. Can make fine-grained, but this is hard work. TM to the rescue! This has been hailed for years, and hardware TM has been around in high-end or prototype hardware for a while. But Intel Haswell now makes TM instructions available in general-purpose CPUs. Basic idea: use cache to track read\/write set, and then use cache coherence to detect conflicts. Limitations: working set is limited (plus something I didn't catch).<\/p>\n<p>They did a comparative study of RTM on real hardware, all the way from programming effort over compiler effects to comparison with traditional sync methods. Some lessons learnt: avoid memory alloc\/dealloc in a TX region, RTM prefers reading to writing, compiler optimizations for removing memory accesses are beneficial inside RTM regions, fallback handler locks should occupy a cache line, different abort events should be handled differently and this should be tuned to the workload. Experiments using skip list from LevelDB (K-V store) using RTM emulator and real Haswell hardware.<\/p>\n<p>Consider the case of insert into a skip list. Naive approach is to wrap the entire insert function into an RTM transaction. However, this failed to make progress at all, due to including memory allocation (for new node) in the critical region. So move the allocation out of the RTM region, compare on emulator and hardware. Vary number of parallel threads, measure TX abort rate. At 16 threads, get ~0.4 abort rate in emulator, but up to 1.6 on 32 threads. On hardware, aborts are much more likely however! Abort rate of 5 at only 4 threads. For another workload (\"1M nodes\"), the emulator failed to work due to cache eviction, but it worked on the hardware! Reason is that L1 on real hardware only tracks write set, while emulator tracks read and write set. So the hardware can tolerate read set cache line eviction.<\/p>\n<p>Compiler study: workload is to insert 100k nodes concurrently to skip list, with different compiler optimizations turned on. Interestingly, things vary pretty wildly here (3x difference in abort rate, and no clear total ordering between optimizations!). Emulator and real hardware show almost opposite behaviour... When investigating reasons, they found that -O1 generates the fewest number of memory access instructions (and can hence outperform -O3).<\/p>\n<p>Combining RTM with a traditional lock that is acquired on the abort path massively increases TX failure rate, and this execution time versus the simple retry approach. Can smarten this up a bit by checking which type of abort occurred (conflict or cache capacity induced), but find that this increases abort rate to ~3.5 at four threads. This is because there's a falsely shared cache line, so add some padding. Now looking much better: 0.17 abort rate instead of 3.5 for four threads!<\/p>\n<p>Finally, compare against traditional sync methods. RTM has about the same performance as fine grained locks or lock-free skip lists.<\/p>\n<p>Limitations by own admission: study limited to data structure behaviour (skip list), only simple micro-benchmarks and limited to 4 threads on real hardware available.<\/p>\n<p>Q: The lock-free version in your comparison appears to have about the same performance as the fine-grained lock version. Are you sure you implemented it right?<br \/>\nA: The lock implementation is optimized (something about having to lock predecessors, didn't catch details).<\/p>\n<p>Q: What about overlapping transactions? Need to take care with boundaries? Does TM really make writing the skip list easier?<br \/>\nA: Provable correctness is easier to attain when using hardware TM (?).<\/p>\n<p>Q (Matthew Grosvenor, Cambridge): Did you do a bottleneck analysis? Specifically, what is the bottleneck of the lock-free version?<br \/>\nA: We have more results showing that lock-free and fine-grained locked version are equivalent in performance up to 40 threads.<\/p>\n<p><em>(ms705)<\/em><\/p>\n<p>&nbsp;<\/p>\n<h3>The nonkernel: A Kernel Designed for the Cloud<\/h3>\n<p><i>Muli Ben-Yehuda, Omer Peleg, Orna Agmon Ben-Yehuda, Igor Smolyar, Dan Tsafrir<br \/>\nTechnion<\/i><\/p>\n<p>Where's the money in OS work? In \"the clouds\". Specifically, in very-short term rentals, i.e. resource micro-charging. Some providers sell \"customizable resource packages\", where prices are set based on supply and demand. Assume this all works out, we still have to deal with aligning economic incentives of cloud providers, clients and the OS (who also needs resources), and somehow manage to share resources reliably and with isolation at fine granularity. How do you build an OS for this kind of environment?<\/p>\n<p>In fact, they claim that there is a single missing piece in historical OS development: architectural support for machine virtualization throughout the system. With this in mind, an OS kernel should not just optimize for performance, but also for cost! Second, the kernel should expose physical resources and get out of the way, giving applications means to manage their own resources while maintaining isolation.<\/p>\n<p>The nonkernel is a hybrid kernel\/hypervisor, and can run on bare metal (being a hypervisor) or on top of a legacy hypervisor (as a guest kernel). Effectively, it does as little as possible, and merely provides little more than hardware-assisted virtualization. It boots the machine, arbitrates contended resources (but only gets involved in the contention case, as I understand it), isolates applications and provides efficient user-space IPC (managing setup and tearndown of channels, it seems). Could build on top of existing OS, or from scratch. Not quite decided on which one yet...<\/p>\n<p>Pros: good performance, zero-overhead virtualization, reduced driver complexity, a more secure system and higher system efficiency due to the integrated economic model.<\/p>\n<p>Cons: clean back, no backwards compatibility, no legacy hardware (need architectural virtualization support), no legacy software.<\/p>\n<p>Preempt question \"isn't this just another Exokernel?\" -- answer: this is Exokernels done right, as the hardware is now in a place where it can better support this and avoid drawbacks (e.g. downloading user code to kernel). Working on prototype, \"nom\".<\/p>\n<p>Q: Relegating lots of functionality to applications. How do you ensure that a malicious application does not compromise the machine?<br \/>\nA: Not trivial to answer this. For DMA, use IOMMU, for other things use architectural virtualization support which we know how to use it safely.<\/p>\n<p>Q: Do I have to rewrite my application to run on nom?<br \/>\nA: You should, but you might not have to. We provide defaults for IO stack, network stack etc. Not for everyone, this is for people who can take advantage of this.<\/p>\n<p>Q (Gernot Heiser, NICTA): How is this different from a minimal hypervisor like NOVA?<br \/>\nA: The big difference is that we allow applications to manage their resources.<br \/>\nQ: This should be easy using just capabilities.<br \/>\nA: No, isn't easy. Applications can dynamically tweak resource requests based on economic model.<\/p>\n<p><em>(ms705)<\/em><\/p>\n<p>&nbsp;<\/p>\n<h2>Session 2: Mobile<\/h2>\n<h3>The Systems Hacker\u00e2\u20ac\u2122s Guide to the Galaxy: Energy Usage in a Modern Smartphone<\/h3>\n<p><em>Aaron Carroll &amp; Gernot Heiser\u00c2\u00a0<\/em><\/p>\n<ul>\n<li><span style=\"line-height: 13px;\">Back in time we published this paper on intrumenting a mobilephone to figure out the power usage.\u00c2\u00a0<\/span><\/li>\n<li>This was great work and we had some nice publications, but the cricicism was that we didn't use a \"real\" device.<\/li>\n<li>The device we used was a \"open moko\" which is a \"free\" phone, kind of designed exactly for this.<\/li>\n<li>But can we do it on a \"real\" phone?<\/li>\n<li>I said \"no\" but I was actually wrong.<\/li>\n<li>We got hold of \u00c2\u00a0a Galaxy S3, totally new at the time, and started to see if we could instrument it.<\/li>\n<li>When you look at power distribution in a phone, there's a battery connected to a power management resistor and then there's a bulk inductor.<\/li>\n<li>It turns out that inductors are quite large physically. So we can attach a sense resistor inline by \"tombstoning\" and \"tee-peeing\" the indocutor with a sense resistor.<\/li>\n<li>So we managed instrument a whole bunch of cool stuff.<\/li>\n<\/ul>\n<p>Things we learned?<\/p>\n<ul>\n<li><span style=\"line-height: 13px;\">This display is super expensive.\u00c2\u00a0<\/span><\/li>\n<li>And looking at video decoding is also reasonably expensive. But what if we did the decoding in software? Very very expensive! Hardware offload is very important.<\/li>\n<li>Android \"power used\" meter is totally inaccurate.<\/li>\n<li>We also looked at measuring the power usage of sensors. The interesting lesson is that sensors in general aren't that expensive. But the software loop used to read the sensors really is.<\/li>\n<li>RAM power isn't that important. Always used in combination with other things. And the CPU\/GPU is much more expensive.<\/li>\n<\/ul>\n<p><span style=\"font-family: 'Helvetica Neue', Helvetica, Arial, sans-serif; line-height: 18px;\">What changed?<\/span><\/p>\n<ul>\n<li>We have a couple of devices. The Galaxy S3, Open Moko and [?..].<\/li>\n<li>In general things haven't changed that much. Idle, cpu without the screen, phonecalls, all roughly the same cost.<\/li>\n<li>BUT - Screen density is increasing rapidly, and this is the most draining resource.<\/li>\n<\/ul>\n<p>(mpg39)<\/p>\n<p>&nbsp;<\/p>\n<h3>The Case for Mobile Forensics of Private Data Leaks:Towards Large-Scale User-Oriented Privacy Protection<\/h3>\n<p><em>Joseph Chan Joo Keng, Tan Kiat Wee, Lingxiao Jiang, &amp; Rajesh Krishna Balan,\u00c2\u00a0Singapore Management University (SMU)<\/em><\/p>\n<p>&nbsp;<\/p>\n<p><span style=\"line-height: 13px;\">Why mobile privacy protection?<\/span><\/p>\n<ul>\n<li><span style=\"line-height: 13px;\">Mobile phones collect tons of data.<\/span><\/li>\n<li>This makes this a treasure trove for malicious people.<\/li>\n<\/ul>\n<p>What about current tools?<\/p>\n<ul>\n<li><span style=\"line-height: 13px;\">They don't really work.\u00c2\u00a0<\/span><\/li>\n<li>And people don't really understand the implications of the the permissions in the app store.<\/li>\n<\/ul>\n<p>We're different:<\/p>\n<ul>\n<li><span style=\"line-height: 13px;\">Because\u00c2\u00a0we analyse logs\u00c2\u00a0forensically\u00c2\u00a0so that we can figure out if a privacy leak has\u00c2\u00a0happened.\u00c2\u00a0<\/span><\/li>\n<\/ul>\n<p>How useful is it? Methodology.<\/p>\n<ul>\n<li><span style=\"line-height: 13px;\">Used TantDroid as a leak detector.\u00c2\u00a0<\/span><\/li>\n<li>Sampled the 10 top apps on the Google play store.<\/li>\n<li>Nexus One using android 2.4<\/li>\n<li>Don't check weather the leaks are valid or invalid, just take them at face value.<\/li>\n<\/ul>\n<p>Results:<\/p>\n<ul>\n<li><span style=\"line-height: 13px;\">226 apps, 105 leaky 48%<\/span><\/li>\n<li>Leaks are start up, user triggered<\/li>\n<li>3 main types of data leaked. IMEI number, course grain cellphone positioning, and IP based positioning.<\/li>\n<li>60% of apps leak data thanks to user actions.<\/li>\n<\/ul>\n<p>Leak Cause Analysis<\/p>\n<ul>\n<li><span style=\"line-height: 13px;\">Instrumented\u00c2\u00a0android to log user events.\u00c2\u00a0<\/span><\/li>\n<li>Used machine learning to classify leaks using WEKA rule miner.<\/li>\n<\/ul>\n<p>Leak prevention mechanism<\/p>\n<ul>\n<li><span style=\"line-height: 13px;\">Display visual notification over leaky aspects of applications visually.<\/span><\/li>\n<\/ul>\n<p>Q (Matthew Grosvenor): You mentioned that you picked the top 10 apps, but your analysis has over 200?<br \/>\nA: As a result of our testing methodology, we ended up with a bunch more applications.<\/p>\n<p>Q: (Aaron, UNSW) It's nice to be able to notify people about leaks, but can you bin applications to stop them leaking? \u00c2\u00a0Some leaks are more serious than others. But disabling leaks \u00c2\u00a0also disables functionality. We want users to have informed consent.<\/p>\n<p><em>(mpg39)<\/em><\/p>\n<p>&nbsp;<\/p>\n<h3>Feasibility Study of Mobile Phone WiFi Detection in Aerial Search and Rescue Operations<\/h3>\n<p><em>Wei Wang, Raj Joshi, Aditya Kulkarni, Wai Kay Leong &amp; Ben Leong National University of Singapore<em><\/em><\/em><\/p>\n<ul>\n<li>Lots of search and rescue operations all the time. 12 per day in the US And lots of people die.<\/li>\n<li>Using drones are expensive and require expert operators.<\/li>\n<li>Cheap hobby drones are available.<\/li>\n<li>Previous work has used visual image recognition to find people, but it requires (heavy) good quality cameras, and good lighting to work.<\/li>\n<li>Our insight? What about using wifi?<\/li>\n<li>Phones regularly scan for WiFi signals, but, scan frequencies vary depending on the mode. This also varies depending on phone manufacturer.<\/li>\n<li>We developed an app to increase scan freq. but to keep the screen off. We can keep the phone running for about 51 hours, which is pretty good. We could push the scan frequency up to 11x with battery life still up to 21hours.<\/li>\n<li>Passive probing: Phones issue small numbers of these frames.<\/li>\n<li>Active probing: If we send lots of RTS (request to send) frames, we can get a CTS (clear to send) response from the phones.<\/li>\n<li>At 15m altitude, our range is about 200m.<\/li>\n<li>Phone orientation matters. Veritcal orientation has better range than horizontal.<\/li>\n<li>Conclusion: Wifi is available, battery life is ok, range is ok.<\/li>\n<\/ul>\n<p>Q: (Gernot) what does it matter if your phone life is 21 hours the quad is only flying for 45mins? A: Use lots of quads.<\/p>\n<p>Q: Why use wifi (1mw) use cellular its 1W! : A: This is a good idea, but the limitation is that cellular harder is heavier (WFT??)<\/p>\n<p><em>(mpg39)<\/em><\/p>\n<p>&nbsp;<\/p>\n<h3>Mobile Applications Need Targeted Micro-Updates<\/h3>\n<p><em><i>Alvin C<\/i><\/em><em><i>heung, Lenin Ravindranath, Eugene Wu, Samuel Madden, &amp; Hari Balakrishnan\u00c2\u00a0MIT CSAIL<\/i><\/em><\/p>\n<p>Why?<\/p>\n<ul>\n<li><span style=\"line-height: 13px;\">We'd like to be able to update our advertising API. But we don't want to wait for people to update their software to use new APIs. Or maybe add new functionality.\u00c2\u00a0<\/span><\/li>\n<li>We want't to be able to make small, parameterized changes to apps. \"Micro-updates\"<\/li>\n<li>You could update the app in the app-store. But there's no push mechanism.<\/li>\n<li>You could have an RPC sever, but the performance cost is high.<\/li>\n<li>You could have an updater built in, but it's expensive.<\/li>\n<li>Parameterised conditions are a pain. We don't only want updates, but we want targeted updates.<\/li>\n<li>Satasuma: Micro-update framework + targeting framework.<\/li>\n<\/ul>\n<p>What?<\/p>\n<ul>\n<li>Code annotations @allowUpdate.<em>\u00c2\u00a0<\/em><\/li>\n<li>Compiler that understands the annotation and embeds the runtime.<\/li>\n<li>Push notifications are sent to awake the runtime to download updates.<\/li>\n<\/ul>\n<p>This is dangerous. How to restrict the class of changes?<\/p>\n<ul>\n<li>Annotations have permissions and scoped pairs.<\/li>\n<li>Updates are only allowed on specific keys.<\/li>\n<li>\"scope\" may be \"all\" - do anything you want, or \"sandboxed\", side effect free statements + whitelisted only.<\/li>\n<\/ul>\n<p>Need to to specify the which devices to apply this to:<\/p>\n<ul>\n<li><span style=\"line-height: 13px;\">Need to decouple the update from the location.\u00c2\u00a0<\/span><\/li>\n<li>We have a table of locations and quires that can be sent back. Devices push locations into the table, then we can push our updates back with SQL like queries.<\/li>\n<\/ul>\n<p>How to apply the updates?<\/p>\n<ul>\n<li><span style=\"line-height: 13px;\">Android automatic updates are nice a but not everyone has it.\u00c2\u00a0<\/span><\/li>\n<li>Android allows dynamic class reloading.<\/li>\n<li>iOS need to use function stubs and an interpreter.<\/li>\n<\/ul>\n<p>Problems:<\/p>\n<ul>\n<li>We'd like to give users the possibility of constraints. \u00c2\u00a0(power usage, privacy etc)<\/li>\n<li>Optimisations - Too many round trips.<\/li>\n<li>Code revisions? - How to you do dependencies, manage versions etc.<\/li>\n<li>Permissions? - How to they compose etc. How do we resolve conflicts.<\/li>\n<\/ul>\n<p>Desktop\/Web might be interesting places to put this to.<\/p>\n<p>Satsuma - Separates targets from names.<\/p>\n<p>&nbsp;<\/p>\n<p>Q: Is a target, just a location? A: Location is useful, but, maybe you want more, is the wifi on, is the application installed.<\/p>\n<p>Q: What about GCM, how it this different? A: GCM requires every developer host their server. Which is expensive and we'd like to generalise this.<\/p>\n<p>Q: How do you know where to annotate? A: Maybe the compiler can set everything to annotated and \u00c2\u00a0then optimise later.<\/p>\n<p><em>(mpg39)<\/em><\/p>\n<p>&nbsp;<\/p>\n<h2>Session 3: OS and Performance II<\/h2>\n<h3>New wine in old skins:\u00c2\u00a0the case for distributed operating systems in the data center<\/h3>\n<p><em><i>Malte Schwarzkopf, Matthew P. Grosvenor, &amp; Steven Hand\u00c2\u00a0University of Cambridge Computer Laboratory &amp; Microsoft Research Silicon Valley<\/i>\u00c2\u00a0<\/em><\/p>\n<p>We make the case that distributed operating systems, an idea from the 1980's are worth a revisiting in the case of the modern operating system.<\/p>\n<p>&nbsp;<\/p>\n<h3>Challenges in the Emulation of Large Scale Software Defined Networks<\/h3>\n<p><em>Arjun Roy, Ken Yocum &amp; Alex C. Snoeren, University of California, San Diego<\/em><\/p>\n<ul>\n<li>Networks impact overall system performance.<\/li>\n<li>Testing in production doesn't really work for networks.<\/li>\n<li>Test beds are ok, but need to be the same size as the real network.<\/li>\n<li>Simulation is ok, but can't run real code.<\/li>\n<li>Emulation allows us to do more accurate models but how?<\/li>\n<li>SDN intro.<\/li>\n<li>Emulation: Mininet-HiFi - Tried to reproduce real results with scaled down networks. 1G -&gt; 10mb\/s. Seems to work for small scale networks? But does it work if you scale up?<\/li>\n<li>But there are issues. Example scenario -\u00c2\u00a03 tiers of machines, front middle and back ends, connected by a switch.<\/li>\n<li>The clogged drain problem: Any given link can have 1000's of flows, but if you shrink the links, you\u00c2\u00a0need to shrink the flows as well.<\/li>\n<li>Flow initiation rate doesn't decrease as quickly as the flows complete as you shrink down the network rate.<\/li>\n<li>Why is this bad? Cache crashing happens as link bandwidth is shrunk. This is contention in the switch.<\/li>\n<li>Flow completion times are a result of the switch contention. Big increase in flow completion times as a result of link shrinking.<\/li>\n<li>It seems like the emulator is lying to us.In this case, it's lying, but it's conservative. But not always.<\/li>\n<li>Straggling herd problem. Emulation spreads out completion times resulting in reduced contention.<\/li>\n<li>Might be tempted to fix the flow table churn. But fixing the clogged drain problem makes the straggling herd problem worse.<\/li>\n<\/ul>\n<p>Shrinking networks can yeild incorrect conclusions, conclusions can be either unrealistically optimistic or pessimistic.<\/p>\n<p><em>(mpg39)<\/em><\/p>\n<p>&nbsp;<\/p>\n<h3>Storage-class memory needs flexible interfaces<\/h3>\n<p><i>Haris Volos, Sankaralingam Panneerselvam, Sanketh Nalli, Michael M. Swift<\/i><\/p>\n<p>SCM technologies: phase-change memory (PCM), spin-transfer torque DRAM, memristors etc. -- all non-volatile RAM technologies. SCMs are as fast as DRAM, but unlike DRAM, they're persistent. Been heralded as the next awesome thing for a while, but might actually be around the corner now.<\/p>\n<p>With SCMs, some things, such as disk request scheduling, become obsolete. As they expose load\/store instruction interfaces, can also get rid of the device driver and a bunch of other layers. Nevertheless, many designs rely on a filesystem atop the SCM devices. This is because FSes provide convenient abstractions for global naming, protected sharing and crash consistency. However, this additional layering can inflate the quick access time to SCMs. For this reason, people have added a fast-path for data, bypassing the FS for bulk operations, and only using the FS for meta-data. However, even meta-data operations matter: 20-50% of time for various workloads (file server, web proxy, web server) is spent doing such operations! For example, a meta-data operation takes about 800ns on RAMFS, which is 10x the access latency of an SCM. Indeed, hierarchical FS traversal can be even more expensive.<\/p>\n<p>So wouldn't it be nice if we could bypass the POSIX abstractions for applications that want to do high-performance SCM access? This is what their <em>Aerie<\/em> library FS provides. The key here is that all meta-data lookup and hierarchy traversal (and thus many meta-data operations) can be done in user-space, without involving the kernel. The only thing that crosses the kernel boundary is the calls into the (specialized) SCM manager. But can't trust user-mode libraries with metadata integrity and sharing leases, so they also have a trusted user-space service that implements this.<\/p>\n<p>Using this libFS structure, they implemented two file systems: a POSIX-like FS, PXFS, for legacy compatibility, and a key-value interface FS, KVFS. Compared these against ext3, and find ~30% latency reduction compared to ext3 on web proxy and file server, but an 18% increase in the web server (likely because of the cost associated with the open() call, which is common in this environment). RAMFS does pretty well too, but KVFS reduces the latency by 66% over ext3 and 16% over RAMFS for the web proxy workload, while giving better guarantees than RAMFS.<\/p>\n<p>Q: Why do you compare with ext3, not ext4? All performance optimization was done on ext4 in recent years, so should look at that to be fair!<br \/>\nA: Will look at in future work.<\/p>\n<p>Q: Presumably application developers will rewrite their applications for SCM. Why do you need to support some of the more arcane legacy APIs (as mentioned in future work)?<br \/>\nA: I guess people will have to rewrite applications if they want to reap the benefits.<\/p>\n<p><em>(ms705)<\/em><\/p>\n<p>&nbsp;<\/p>\n<h3>Optimizing RAM-latency Dominated Applications<\/h3>\n<p><i>Yandong Mao, Cody Cutler, &amp; Robert Morris<br \/>\nMIT CSAIL<\/i><\/p>\n<p>RAM latency can dominate application performance, for example if you need to follow long pointer chains or the working set exceeds cache size. Lots of cache misses lead to many memory accesses and load on the memory bus. Their solution is to treat RAM more like a disk (but with different latency magnitude), and apply the same optimization techniques: batching, sorting, pipelining etc.<\/p>\n<p>Experimental environment: six-core Xeon X5690, one memory controller with three channels that each have a row buffer cache inside them. It also supports a bunch of prefetching features (in hardware and software), parallelism across channels and executes instructions out-of-order. Note that row buffer cache hits are 2-5x faster than misses, and sequential access has 3.5x higher throughput than random access.<\/p>\n<p>Consider a garbage collector example: long pointer chains, but with no predictability of next locality. So each access ends up generating a cache miss and stalls for RAM access. Linearisation of requests could help here, so on each GC cycle, arrange objects in tracing order, and make use of prefetcher. For 1.8 GB working set of HSQLDB, found that sequential order tracing is 1.3x faster than random order. In future work, would like to use a better linearization algorithm than copy collection.<\/p>\n<p>Second example is using Masstree: for this key-value store, it is not possible to linearize memory accesses, as the storage abstraction is a shared B-tree. Despite careful design, Masstree is still RAM latency-dominated, as each key lookup follows a random path. To improve this, use batching and interleaving of tree lookups. Specifically, they use software prefetching to interleave tree lookup and RAM fetch. On a single core, this interleaving strategy can improve the performance by 30% with a batch size of five.<\/p>\n<p>Parallelization also helps, as the RAM can actually fetch stuff in parallel, so using more cores helps. Up to 12 hyperthreads, the total number of RAM loads scales linearly with the Masstree throughput! Can also combine parallelization and interleaving, and still get 12-30% improvement over just parallelization, although this tails off with more threads.<\/p>\n<p>Conclusions: interleaving seems more general than generalization, but is more difficult than parallelization, especially if we try to do it automatically and without programmer input (might be impossible without some help). Found that interleaving technique can also be applied to hashtable, which receives at 1.3x throughput boost (for memcached). Would also be nice to have tools to identify RAM stalls -- they had to use an indirect technique based on function costs and function operations.<\/p>\n<p>Q: You propose two techniques that can improve RAM access throughput. But they're highly tailored towards the application and data structures. How do you think you can generalize your techniques or make them application-independent?<br \/>\nA: Don't claim that all of them can be applied to all applications. But categories of techniques might work for categories of applications, so something of a pattern-based approach might work.<\/p>\n<p><em>(ms705)<\/em><\/p>\n<p>&nbsp;<\/p>\n<h2>Optimizing the File System with Variable-Length I\/O for Fast Storage Devices<\/h2>\n<p><i>Yongseok son, Jae Woo Choi, Hyeonsang Eom, &amp; Heon Young Yeom,\u00c2\u00a0Seoul National University<\/i><\/p>\n<p>&nbsp;<\/p>\n<p>Motivation:<\/p>\n<ul>\n<li>Lots of fast SSD storage devices are around<\/li>\n<li>Median file size<\/li>\n<li>in the desktop is about 4kbB Cloud and HPC 25%-40% of files &lt;4kB .<\/li>\n<li>Fast storage has poor performance on small sizes.<\/li>\n<li>HDD vs SSD\n<ul>\n<li>HDD - Mechanical overhead == Request size no affect on overall latency.<\/li>\n<li>SSD - Seektime between 0.08 and 0.16ms - Affects overall latency.<\/li>\n<\/ul>\n<\/li>\n<li>Usually a syscall for 1kB read results in a 4kb read. [Block read as per HDD]<\/li>\n<li>Linux VFS masks request size at byte-granularity with page-size granularity.<\/li>\n<li>Results in fetching unnecessary data.<\/li>\n<\/ul>\n<p>Approach:<\/p>\n<ul>\n<li><span style=\"line-height: 13px;\">Extend the I\/O subsystem to to include byte granularity information.\u00c2\u00a0<\/span><\/li>\n<li>Use sub page management module.<\/li>\n<li>Sub pages are managed using a bitmap and a worker thread to sync.<\/li>\n<\/ul>\n<p>Results:<\/p>\n<ul>\n<li><span style=\"line-height: 13px;\">Read operations &lt;4kb \u00c2\u00a01.3-2.6x faster.\u00c2\u00a0<\/span><\/li>\n<li>Write operations 3.7-6.3x faster.<\/li>\n<li>Write operations &gt;= 4kb. Faster.<\/li>\n<\/ul>\n<p>&nbsp;<\/p>\n<p>Q: Have you sent you patch into the linux kernel? A: No.<\/p>\n<p>Q: Is you dataset random or real? A: random; C: This is unfair as linux is optimistically caching.<\/p>\n<p>&nbsp;<\/p>\n<h2>RevDedup: A Reverse Deduplication Storage System Optimized for Reads to Latest Backups<\/h2>\n<p><i>Chun-Ho Ng &amp; Patrick P. C. Lee ,\u00c2\u00a0<\/i><i>The Chinese University of Hong Kong<\/i><\/p>\n<p>&nbsp;<\/p>\n<p>Motivation:<\/p>\n<ul>\n<li>VM image checkpointing is common, but data exploding. Growing faster than disk cost is shrinking.<\/li>\n<li>Thus, use reduplication.<\/li>\n<li>Most people use inline instead of out-of-order dedup.<\/li>\n<li>But inline dedup causes fragmentation. Lots of seek operations.<\/li>\n<li>Other people have looked a this 1) selective rewrites and 3) container capping and prefetching.<\/li>\n<li>All previous work done on simulation.<\/li>\n<\/ul>\n<p>Our work:<\/p>\n<ul>\n<li><span style=\"line-height: 13px;\">Goal - Mitgate fragmentation for read on latest backups.\u00c2\u00a0<\/span><\/li>\n<li>Contributions - Hybrid of inline and out-of-order.<\/li>\n<li>Two phase reduplication used. Course-grain dedup. But fine-grain d-dedup.<\/li>\n<\/ul>\n<p>Global dedup.<\/p>\n<ul>\n<li><span style=\"line-height: 13px;\">Segments are\u00c2\u00a0several\u00c2\u00a0MB in size.\u00c2\u00a0<\/span><\/li>\n<li>Tries to apply in the version, different versions of the same VM and different versions of the different VMs.<\/li>\n<li>Small memory usage for indexing.<\/li>\n<li>Mitigate fragmentation by using reading to amortize the cost.<\/li>\n<li>Reverse dedup on early versions of the<\/li>\n<li>Shared segments<\/li>\n<\/ul>\n<p>[Sorry, fell asleep, not because I wanted to. Jetlag + all night hacking the CamIO demo]<\/p>\n<p>(mpg39)<\/p>\n<h2><\/h2>\n<h2>TinyFTL: An FTL Architecture forFlash Memory Cards with Scarce Resources<\/h2>\n<p><i>Jongmin Lee, Yongseok Oh, Hunki Kwon, Jongmoo Choi, Donghee Lee, &amp; Sam H. Noh,\u00c2\u00a0Dankook University, University of Seoul &amp; Hongik University<\/i><\/p>\n<p>&nbsp;<\/p>\n<ul>\n<li><span style=\"line-height: 13px;\">Flashmemory is key to lots of things.\u00c2\u00a0<\/span><\/li>\n<li>This paper looks at flash memory cards.<\/li>\n<li>The main difference is the resources. Onboard cards are small micros with very little RAM.<\/li>\n<li>Flash memory is unique because it can't be overwritten, data can be relocated, but to erase, entire blocks must be erased at one time.<\/li>\n<li>The mapping between segments and data is stored in a table also on flash.<\/li>\n<li>Short version - Flash storage requires caching and garbage collection.<\/li>\n<li>This is done by the FTL - Flash Translation Layer<\/li>\n<\/ul>\n<p>We propose:<\/p>\n<ul>\n<li><span style=\"line-height: 13px;\">TinyFTL -\u00c2\u00a0Target\u00c2\u00a0is mobile storage.\u00c2\u00a0<\/span><\/li>\n<li>Need to minimise resource usage.<\/li>\n<\/ul>\n<p>Description:<\/p>\n<ul>\n<li><span style=\"line-height: 13px;\">FTL uses a summary page located in the last page of each block.\u00c2\u00a0<\/span><\/li>\n<li>The overhead of the summary page is negligible.<\/li>\n<li>In comparison to DFTL (current popular) TinyFTL uses summary pages as well as checkpoints.<\/li>\n<li>TinyFTL does efficient garbage collection. Three optimisation points:\n<ul>\n<li>Computation for victim blocks: \u00c2\u00a0DFTL \u00c2\u00a0compares the whole block. TFTL uses a window with a small valid count field from the summary page. Resulting in much lower computation.<\/li>\n<li>Memory usage:\u00c2\u00a0\u00c2\u00a0DFTL valid counts grow linearly with size of device. Using windows means TFTL scales better.<\/li>\n<li>?<\/li>\n<\/ul>\n<\/li>\n<\/ul>\n<p>Results:<\/p>\n<ul>\n<li>Done in simulation from ESMC<\/li>\n<li>Three benchmarks - Financial, MSN and something<\/li>\n<li>\u00c2\u00a0TFTL does better on all of the benchmarks.<\/li>\n<li>TFTL also does better on bootup.<\/li>\n<\/ul>\n<p><em>(mpg39)<\/em><\/p>\n<p>&nbsp;<\/p>\n<h2>Security bugs in embedded interpreters<\/h2>\n<p><i>Haogang Chen, Cody Cutler, Taesoo Kim, Yandong Mao, Xi Wang, Nickolai Zeldovich, Frans Kaashoek<br \/>\nMIT CSAIL<\/i><\/p>\n<p>Interpreters are everywhere these days, from the Linux kernel to Type 1 font renderers. Vulnerabilities in interpreters are also ubiquitous. Consider the example of a packet filter, e.g. for tcpdump. Could run the whole filter in user space, which is safe but slow. Could also run in the kernel, but then we have untrusted user space code in the kernel. Traditional solution: Berkeley Packet Filter (BPF) + interpreter. This seems sound: the interpreter runs in the kernel, and byte code comes from user space. But byte code and input data are still untrusted, and if a malicious user was to inject malformed code or data, bugs in the interpreter can compromise the kernel. There are real examples of this: e.g. the INET_DIAG infinite loop vulnerability -- DoS as a result of passing in a zero \"oplen\" parameter via BPF. Second example: ClamAV anti-virus signed division vulnerability, where a parameter check was implemented incorrectly and ended up with the interpreter trapping as a result of division by zero. Finally, third example is an arbitrary code execution vulnerability in FreeType font interpreter: by passing a negative argument count, can manipulate interpreter stack pointer and thus break into system.<\/p>\n<p>Conclusion: writing secure interpreters is hard! Rest of talk will discuss some security guidelines for writing interpreters.<\/p>\n<ul>\n<li>Best option is to not have an interpreter at all, but let's assume we do need one.<\/li>\n<li>One option is to make the interpreter non-embedded and run it in a separate process (exceptions when this won't work: high performance required, or interpreter in kernel).<\/li>\n<li>Keep the byte code as simple and least expressive as possible, to avoid as many possible pitfalls as possible. Don't overdesign!<\/li>\n<li>Limit resource use (e.g. interpreter runtime, memory etc.) to avoid DoS of the host system.<\/li>\n<li>Don't allow calling into external host system functions from byte code, as this can easily lead to arbitrary code execution vulnerabilities (as e.g. in Python's pickle interpreter).<\/li>\n<\/ul>\n<p>What research opportunities are there? Automated testing of embedded interpreters. Could do static analysis, but the invariants are too dynamic and complicated. Could do symbolic testing, but control flow and complexity highly depends on the byte code. Or maybe we can build a reusable general embedded interpreter, e.g. based on Java byte code or something.<\/p>\n<p>Q: Did you find *any* good interpreter that didn't have any of these problems? Is there any good citizen?<br \/>\nA: Of course, but this doesn't mean it can't have these problems in the future.<\/p>\n<p>Q: You know that JVM has a theorem prover that detects bad byte code that runs on bytecode before executing it?<br \/>\nA: Our goal is not to analyze general-purpose byte code machine interpreters.<\/p>\n<p>Q: You mention constraining resources. How would you actually do that?<br \/>\nA: [missed the answer]<\/p>\n<p>Q: For OS kernel code, it's hard to enforce security as there's one big address space. What could one do to OS design in order to make embedded interpreters in the kernel safe?<br \/>\nA: Could do micro-kernel style interpreter-in-userspace. But if need performance, nothing you can do beyond making sure the interpreter is correct.<\/p>\n<p><em>(ms705)<\/em><\/p>\n<p>&nbsp;<\/p>\n<h2>Making Automated Testing of Cloud Applications an Integral Component of PaaS<\/h2>\n<p><i>Stefan Bucur, Johannes Kinder, George Candea<br \/>\nEPFL<\/i><\/p>\n<p>PaaS (AppEngine and friends) is jolly good, as it's easy to use. But how does one test these applications systematically? Consider the example of a simple trivia Q&amp;A service. Could do unit tests or integration tests. But constructing test inputs is a bit tedious, as we need to wrap them into tons of boilerplate (XML etc.). Even harder is generating all the inputs, and getting full coverage is almost impossible. Integration tests focus on corner case, and can come up with lots of these and yet not cover all of them.<\/p>\n<p>Wouldn't it be nice if there was an automated way of generating tests, especially if this was offered as a service with PaaS application deployment? Developer just submits code and input description, and then \"the cloud\" performs test case generation, testing etc. Could somehow use symbolic execution for doing the test case generation (using a constraint solver). But real web apps are more complex, and do not just take primitive types as input. This now makes the parser and the symbolic execution tree a lot more complex (or at least bigger). What's worse, the fuzz test case generator may end up exercising all kinds of exceptions in e.g. the JSON parser, but won't trigger the cases exercising bits of our app that we're interested in. Their solution to this is something called \"layered symbolic execution\", which essentially replaces the output of the parsing with a \"fresh\" variable. Unfortunately, the variable now doesn't contain a valid JSON string though. They use an \"onion object\", which is the input description submitted by the user, to then synthesize reasonable values.<\/p>\n<p>Prototype with GAE dev server and S2E symbolic virtual machine. Currently WIP, can generate one test case per second.<\/p>\n<p>Q (Matthew Grosvenor): What in this work makes it specific to cloud applications? Could this be used in general applications as well?<br \/>\nA: What's specific is the onion-style layered inputs, but could in principle work for other applications too.<\/p>\n<p>(ms705)<\/p>\n<p>&nbsp;<\/p>\n<h2>Optimizing unit test execution in large software programs using dependency analysis<\/h2>\n<p><i>Taesoo Kim, Ramesh Chandra, Nickolai Zeldovich<br \/>\nMIT CSAIL<\/i><\/p>\n<p>Unit tests are important, but running them takes too long (e.g. 10 minutes in Django). This work makes them fast (2s).<\/p>\n<p>Research direction here is to do regression test selection (RTS), which is to run only the necessary tests instead of everything. This requires syntactical analysis of test cases and code changes, and resolving the appropriate tests to run. But RTS techniques are never adopted in practice. Hypothesis: \"soundness\" (no false negatives) ends up killing their benefits. For example, if you change a global variable, this could affect (and thus re-run) everything, in which case we may as well never have used RTS in the first place. The goal of this work is to make RTS practical, by prioritising performance over soundness and better integrating it with the development cycle.<\/p>\n<p>To track which tests execute which functions, first need to figure out dependencies between functions. Also incrementally update this dependency information as unit tests run, and these increments can be pushed to the repo server alongside code changes (so that other people only need to run the affected tests when they sync these changes?).<\/p>\n<p>Still have the false negative problem, so need to do a better job at dependency identification. They introduce an asynchronous test server that actually runs all tests continuously, and monitors them for any missed false negatives (example: non-deterministic control flow leading to function only being called sometimes).<\/p>\n<p>Evaluation: using Django and Twisted frameworks, and looked at last 100 commits to trunk. Find that sometimes, small modifications to \"hot\" functions lead to tons of unit tests being re-run, and sometimes large-scale changes end up re-running few cases (didn't quite understand why this was). In terms of test runtimes, they go from minutes to seconds as a result of introducing TAO (their stuff). Downside (ish): TAO adds extra stuff to code base, ranging from 60 to 117% of original repo size! But could reduce this maybe.<\/p>\n<p>[no questions]<\/p>\n<p><em>(ms705)<\/em><\/p>\n<p>&nbsp;<\/p>\n<h2>Lazy Tree Mapping: Generalizing and Scaling Deterministic Parallelism<\/h2>\n<p><i>Yu Zhang &amp; Bryan Ford<br \/>\nUniversity of Science and Technology of China &amp; Yale University<\/i><\/p>\n<p>Many-core hardware now abundant, but parallelism makes life hard due to non-determinism. Data races and non-determinism are everywhere! Can just accept this and live with it, or use race detectors, or use deterministic schedulers. Ideally, we'd like to develop a parallel programming model in which races do not exist in the first place. Determinator tries to this this, but isn't very general. Their previous work, SPMC, enabled producer-consumer page sharing under deterministic parallelism. However, this was very wasteful in terms of space. Also introduced DetMP, which is a deterministic message-passing API with explicit SPMC (single producer, multiple consumer) channels.<\/p>\n<p>In this work, they introduce Lazy Page Mapping and Tree-style Mapping, which are both optimizations to make SPMC sharing better. Available as an extension to Determinator (xDet) and on top of Linux (DLinux). Performance is much better than previous work for various MPI workloads.<\/p>\n<p><em>(ms705)<\/em><\/p>\n<p>&nbsp;<\/p>\n<p>That's it, folks!<\/p>\n","protected":false},"excerpt":{"rendered":"<p>Matt and myself are at the Asia-Pacific Systems Workshop today, presenting our paper on distributed operating systems in data centers, and we&#8217;ll be live-blogging the workshop for you.<\/p>\n","protected":false},"author":2,"featured_media":0,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":[],"categories":[6],"tags":[85,79,35],"_links":{"self":[{"href":"https:\/\/www.syslog.cl.cam.ac.uk\/wp-json\/wp\/v2\/posts\/1222"}],"collection":[{"href":"https:\/\/www.syslog.cl.cam.ac.uk\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/www.syslog.cl.cam.ac.uk\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/www.syslog.cl.cam.ac.uk\/wp-json\/wp\/v2\/users\/2"}],"replies":[{"embeddable":true,"href":"https:\/\/www.syslog.cl.cam.ac.uk\/wp-json\/wp\/v2\/comments?post=1222"}],"version-history":[{"count":28,"href":"https:\/\/www.syslog.cl.cam.ac.uk\/wp-json\/wp\/v2\/posts\/1222\/revisions"}],"predecessor-version":[{"id":1224,"href":"https:\/\/www.syslog.cl.cam.ac.uk\/wp-json\/wp\/v2\/posts\/1222\/revisions\/1224"}],"wp:attachment":[{"href":"https:\/\/www.syslog.cl.cam.ac.uk\/wp-json\/wp\/v2\/media?parent=1222"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/www.syslog.cl.cam.ac.uk\/wp-json\/wp\/v2\/categories?post=1222"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/www.syslog.cl.cam.ac.uk\/wp-json\/wp\/v2\/tags?post=1222"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}